1. Field of the Invention
The present invention relates to time delay and integrate sensors (TDI sensors). In particular, the invention relates to a new charge transfer device that is compatible with usual CMOS (complimentary MOS) sensor processing techniques for better integration with CMOS processing.
2. Description of Related Art
Image sensors for Time Delay and Integration (TDI) applications are usually implemented with a CCD (charge coupled device) architecture. TDI image sensors are used in line scan applications where the light level is low or where the speed of the moving image is high. The CCD is clocked so that the charge packets move across the sensor synchronously with the image. In this way, photo-charges generated by particular parts of the image are accumulated in corresponding charge packets as the charge packets are transferred across the sensor. This increases the sensor""s sensitivity in low light situations. The conversion from an electron signal to a voltage is done as the charge packets are transferred out of the last row.
Charge transfer cannot typically be achieved in CMOS sensors that are fabricated with CMOS processes. CMOS image sensors can provide many advantages over CCDs, however it is difficult to achieve charge transfer within these devices and this has prevented CMOS image sensors from being configured for TDI operation.
On the other hand, charge transfer within CCDs is possible because of the presence of more than one electrically isolated gate electrode formed of a polycrystalline silicon layer. In CCD processes, these multiple layers are allowed to form overlapping CCD gate electrodes for use in plural phase structures (e.g., three or four phases) in a CCD or in structures where the overlap helps form a potential gradient to define the transfer direction (e.g., as in a two phase structure). The modifications that would be required to implement distinct and overlapping polycrystalline silicon layers in a CMOS process are prohibitive. xe2x80x9cVirtual phasexe2x80x9d techniques (a form of single phase charge transfer) are known to have previously been used in CCD image sensors. For example, see U.S. Pat. Nos. 4,779,124 and 4,229,752, incorporated herein by reference, both granted to Hynecek.
It is an object of the present invention to provide a device that achieves charge transfer within a sensor processed using a CMOS manufacturing process which does not require any additional polycrystalline silicon layers as may be found in a typical CMOS process.
These and other objects are achieved in a single phase CCD transfer device that is formed in a substrate of a first conductivity type. The device includes a gated region and a photo-diode region. The gated region includes a gated part formed in the substrate and a gate electrode insulatively spaced over the gated part. The photo-diode region has proximal and distal sides and includes first, second and third diode sub-regions. The proximal side is adjacent to the gated region. The second diode sub-region is formed of a second conductivity type in the substrate; the third diode sub-region is formed of the first conductivity type in the second diode sub-region in the proximal side; and the first diode sub-region is formed of the first conductivity type in the second diode sub-region in the distal side. The first and third diode sub-regions contain different dopant concentrations of a same species so as to generate an internal field that induces charge carriers to drift to the proximal side. The first and third diode sub-regions are formed without self-alignment but sufficiently close as to fringe out either a barrier or a pocket in a potential profile between the distal and proximal sides of the diode region. The gated part is either a buried channel gated part or a surface channel gated part. The buried channel gated part includes a channel of the second conductivity type formed in the substrate and a first gated sub-region formed in the channel with a compensating inclined angle implant that undercuts the gate electrode with a dopant species of an opposite polarity to the polarity of the channel implant. A remaining portion of the channel and the first gated sub-region are of the same conductivity type but provide different densities of majority carriers. The surface channel gated part includes a first gated sub-region formed in the substrate by an inclined angle implant that undercuts the gate electrode with a dopant species of the same type as the dopant species in the substrate. A remaining portion of the gated part is a sub-portion of the substrate.